Clan x86

Technical (Development, Security, etc.) => General Programming => Topic started by: Nate on April 20, 2008, 04:23:24 pm

Title: Verilog(VHDL)
Post by: Nate on April 20, 2008, 04:23:24 pm

It is the ugliest, most horrible thing I have ever touched.  Does anyone have any experience in it, or suggestions that may prove useful?  Half the syntax seems to be optional in most cases and the only help we get in from a grad student who speaks little english.

Title: Re: Verilog(VHDL)
Post by: Chavo on April 20, 2008, 05:56:35 pm

http://www.x86labs.org/forum/index.php/topic,11044.0.html