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Verilog(VHDL)

Started by Nate, April 20, 2008, 04:23:24 PM

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Nate

April 20, 2008, 04:23:24 PM
It is the ugliest, most horrible thing I have ever touched.  Does anyone have any experience in it, or suggestions that may prove useful?  Half the syntax seems to be optional in most cases and the only help we get in from a grad student who speaks little english.

Chavo

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April 20, 2008, 05:56:35 PM
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